What’s a preeminent chip company to do when its process node technology lags the competition by (roughly) one generation, but outmoded naming conventions make it seem like it’s two nodes behind? For Intel, the response was to change how it refers to its nodes with the aim of better reflecting its positioning within the leadership semiconductor manufacturing space.
Intel revealed its new node nomenclature, and showcased changes to its process and packaging roadmaps during its “Intel Accelerated” webcast, streamed live yesterday afternoon. In his second major such event since joining Intel in February, CEO Pat Gelsinger filled in a lot of detail for the company’s “IDM 2.0 strategy” – its bold multi-pronged plan to achieve process parity with its competitors by 2024 and leadership in 2025.
“Intel, like the rest of the industry, has recognized that we need to evolve the way we talked about process nodes,” said Gelsinger. “These days, the various naming and numbering schemes used across the industry – including ours – no longer refer to any specific measurement and don’t tell the full story of how to achieve the best balance of power, efficiency and performance.”
The new naming structure starts with the node that comes after 10nm SuperFin, which is used for (mobile chip) Tiger Lake and Xe GPU products, including the forthcoming Xe-HPC product, Ponte Vecchio. That next node, previously known as 10nm Enhanced SuperFin (it’s also been called 10nm+++ and 10nm++), will now be known as “Intel 7.”
“[With Intel 7], we’re expecting an approximately 10 to 15 percent performance-per-watt increase over 10nm SuperFin,” said Ann Kelleher, senior vice president and general manager of technology development. “As we evolve the node with additional transistor level optimizations, this is equivalent to a full node of performance gain. As a result, we believe that Intel 7 is an appropriate name to help customers understand the kind of competitive performance being delivered by the node.”
Intel 7 will begin shipping first on the client side with Alder Lake in 2021, and the server product Sapphire Rapids will be in production in the first quarter of 2022, said Kelleher.
Next on the roadmap, Intel 4 is slotted for production in the second half of 2022 with product shipping starting in 2023. Intel 4 products include Meteor Lake for client and Granite Rapids for the datacenter. This is the node previously known as 7nm. Intel says it taped the Meteor Lake client compute tile last quarter (Q2 2021).
“Beyond the actual wafer, we’re right where we expect to be relative to our performance and defect density expectations,” said Kelleher. “Indeed, our defect density trend is on the right path to meet our product commitments.”
Intel 4 is the first Intel node to make wide use of extreme ultraviolet lithography (EUV).
Next on the new roadmap is Intel 3, set to debut in the second half of 2023. Intel 3 will deliver around an 18 percent transistor performance-per-watt increase over Intel 4, according to the company, thanks to improvements in power and area. It’s a higher level of improvement than a standard full node improvement, noted Kelleher, citing early modeling and test chip data.
Enhancements include the addition of a denser, higher performance library, increased intrinsic drive current to optimize the FinFET transistor, an optimized interconnect metal stack with reduced via resistance and increased use of EUV compared to Intel 4.
“The angstrom era” brings more name changes
The surprise on the roadmap is Intel 20A, where the A stands for “angstrom.” It’s intended to – in Gelsinger’s words – “evoke a new era, where we are crafting devices and materials at the atomic level, the angstrom era of semiconductors.” 1 angstrom is equal to 0.1 nanometers; however, in Intel’s branding parlance, angstrom is not representative of a single discrete metric but rather a “bundled” performance measure relative to the preceding generation.
With a planned introduction in 2024, Intel 20A features two new technologies: a new transistor gate-all-around architecture called RibbonFET and a backside power delivery mechanism, called PowerVia.
“RibbonFET is Intel’s implementation of a gate-all-around transistor. The technology delivers faster transistor switching speeds while achieving the same drive current as multiple fins in a smaller footprint,” said Intel.
“PowerVia is Intel’s unique industry-first implementation of backside power delivery, optimizing signal transmission by eliminating the need for power routing on the front side of the wafer,” the company said.
Following 20A, Intel 18A is in development for early 2025 with refinements to RibbonFET that will further drive increased transistor performance, said Intel’s Sanjay Natarajan, senior vice president and co-general manager, logic technology development.
Intel is also planning to usher in new lithography advances in 2025. The next generation of EUV tools is known as high numerical aperture EUV, or high-NA. High-NA will integrate even higher precision lenses and mirrors, improving resolution and allowing for even smaller features to be printed on the silicon, said Intel.
Farther out on the horizon, Intel has plans to advance gate-all-around and backside power. Noting the R&D is “already in the works,” Kelleher said Intel is already working on future nodes beyond 2025 that utilize stacked NMOS and PMOS.
Packaging — What’s next for EMIB and Foveros
The company is also announcing new packaging innovations as part of its IDM 2.0 strategy. With chip development moving to a tiled or chiplet approach, innovative packaging is required to connect all the pieces into a unified device. Following the release of its EMIB (embedded multi-die interconnect bridge) and the Foveros die-stacking technology, Intel will be introducing its third-generation Foveros product, Foveros Omni, and new companion technology Foveros Direct.
Where Foveros enables mixing and matching of chiplet devices that Intel calls “tiles,” in one plane, Foveros Omni takes the concept to the next level, allowing integration of multiple disaggregated top tiles with multiple base tiles across mixed fab nodes. Volume manufacturing is to begin in 2023, according to Intel.
“Foveros Omni uses a combination of through silicon via (TSV) and through package copper columns to balance high speed signal and power delivery with dense die-to-die interconnect,” said Babak Sabi, Intel corporate vice president and general manager of assembly and test technology development. “It improves on the original Foveros with die-to-die interconnect starting at 36 micron and scaling down to 25 micron micro bump pitch.” This quadruples bump density to 1,600 IOs per mm2, while delivering the same interconnect power of Foveros at .15 picojoules per bit, he added.
Foveros Direct is complementary to Foveros Omni and launches in the same 2023 timeframe. The technology uses solderless direct copper-to-copper bonding to enable low-resistance interconnects. Foveros Direct enables sub-10-micron bump pitches, providing an order of magnitude increase in the interconnect density for 3D stacking, according to Intel.
“The resulting capability of 10,000 IOs per mm2 opens up new concepts for functional die partitioning that were previously unachievable,” said Sabi. For example: the ability to have multi-level cache for on-die logic stacking at very low latency and without any power penalty.
“We are blurring the lines between where the wafer ends and where packaging begins,” said Sabi.
Sapphire Rapids (now an “Intel 7” product) will be the first Intel Xeon datacenter product to ship in volume with EMIB. The next generation of EMIB will move from a 55 micron bump pitch to 45 microns, followed by a third generation that will have a 40 micron bump pitch. Intel’s Ponte Vecchio GPU would be the first product to use both EMIB and the second-generation Foveros, which implements a bump pitch of 36 micron.
New Customers for Intel Foundry Services: AWS and Qualcomm
Intel’s Foundry Service (IFS) business, launched in March, has its first publicly named customers: AWS and Qualcomm. AWS is the first customer to use IFS packaging solutions, while Qualcomm will be a partner on the future 20A process technology. “Both Intel and Qualcomm believe strongly in the advanced development of mobile compute platforms, and ushering in a new era in semiconductors,” said Gelsinger.
The CEO added that Intel has over 100 customers in its IFS pipeline. “Those engagements are progressing very well,” he said. “Some of those are for the packaging technologies like our AWS announcement, some of those are what I call modern nodes, Intel 16, or 16nm process, and there’s a lot of interest in Intel 20A, and Intel 18A.”
Characterizing the prospective customers, Gelsinger said “some are very traditional names, some might be seen as competitors of ours in the past, but now we’re working with them…, some are industrial and auto companies, and there are other semiconductor companies that need a foundry opportunity to leverage, as well as others in the industry.”
The company also announced that Intel InnovatiON will be a fully hybrid event, held in San Francisco and online Oct. 27-28, 2021. More information is available at the Intel ON landing page.
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